The scaling of semiconductor technology (CMOS) has been the driving force for the success of information technology. However, as device dimensions continue to shrink into the nanometer length-scale regime, conventional semiconductor technology is approaching fundamental physical limits. For example, the increasing power dissipation on the chip level is one of the key challenges today. Rising leakage currents and the increasing difficulty to further reduce the supply voltage have impacted the passive and active power dissipation, limiting the overall performance. Therefore a key attribute of any new device that may be considered for replacing the conventional FET is reduced power dissipation. In that respect new strategies, including the use of III-V as well as novel materials and 1D-device concepts including innovative device architectures and device concepts need to be explored and assessed. They are crucial to extend the current capabilities and maintain momentum beyond the time frame of the silicon technology roadmap. This presentation will outline the challenges of current semiconductor roadmap and will evaluate in more detail the most prominent candidates for becoming the next nanoelectronic switch.